There has been known a dynamic RAM including a voltage generator circuit including charge pump circuits for producing a back bias voltage to be supplied to a substrate of the RAM and a boosting voltage to generate a selection voltage boosted for a word line of the RAM. Described in the JP-A-3-214669 is an example of such dynamic RAMs. In this dynamic memory described in JP-A-5-291534, the substrate voltage is set to 0 volt (V), the data line has a high-level potential of 2 V and a low-level potential of 1 V, and the word line possesses a selection level of 3 V. In the "ISSCC '94/Session 8/DRAMs and Non-Volatile Memories/Paper TA 8.2", there has been described a boosted sense-ground technology. Described in the JP-A-7-57461 is a technology related to a memory array in which the amplitude of data line voltage is set such that the high and low levels of data line are respectively set to 1.5 V and 0 V and the amplitude of word line voltage is selected such that the high and low levels of word line are respectively set to 2 V and -0.5 V. In the JP-A-5-12866, there has been described a dynamic RAM in which neither a substrate biasing circuit nor a word boosting circuit are employed. Disclosed in the JP-A-7-240093 is a dynamic RAM in which a memory array including bit lines, a memory cell, and a sense amplifier are supplied with a low-level potential higher than the ground potential of the RAM chip.
A dynamic memory cell includes address selecting metal-oxide field-effect transistors (MOSFETs) and an information storing capacitor to achieve information storage operation according to presence or absence of electric charge in the capacitor. To keep information in the form of charge for a long period of time, it is required to supply a negative back bias to a substrate gate (corresponding to a channel region) on which the address selection MOSFETs are fabricated so as to increase the value of the effective threshold voltage of the MOSFETs.
In such MOSFETs which constitute a peripheral circuit to achieve an operation to select an address of the dynamic memory cell and which constitute a sense amplifier and a main amplifier, when a negative back bias voltage is supplied to the substrate gate, the threshold voltage is increased according to the supplied voltage. This leads to reduction in conductance in the on state thereof and hence the operation speed of the circuit is accordingly lowered. To avoid this drawback, there has been proposed a method in which the negative back bias voltage above is applied to the memory array section including the dynamic memory cells. However, in such a case in which, for example, to apply different bias voltages respectively to a substrate of the memory array section and a substrate of the peripheral circuit section, it is required to separate a well region as a substrate of the memory array section and a well region as a substrate of the peripheral circuit section. This disadvantageously complicates the production process of the semiconductor devices.
In a high-level write operation for the dynamic memory cell, since the information storage capacitor is charged up via the address selection MOSFET, it is necessary to set the gate potential of the MOSFET to an appropriate level. When this operation is not conducted, the charge-up level is lowered according to the voltage corresponding to the threshold voltage of the MOSFET and hence the amount of information charge is reduced. To prevent the level reduction, the selection level of the word line connected to the gate of the MOSFET is set to a voltage obtained by adding at least the threshold voltage to the high-level voltage applied to the bit line. As above, in the conventional dynamic RAM, there is required the voltage boosting operation for the word line selection. To generate such the boosting voltage for the word lines and the substrate back bias voltage, there are respectively required charge pump circuits. This resultantly leads to drawbacks of a relatively large area increase in current consumption current.